123 School Work

Scaled down MOSFETS

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  AN IDEALLY SCALED-DOWN PARTIALLY-DEPLETED SOI CMOS CONCEPT FOR 90nm NODE AND BEYOND
  
  H. Dang, T. Matsumoto, K. Eikyu, K. Ota, Y. Hirano, T. Iwamatsu, T.Ipposhi, S. Maegawa, and Y. Inoue
  
  
  Abstract
       In this paper, we present an ideal concept of scaling down partially-depleted silicon on insulator (PD-SOI) CMOS for 90nm node and beyond...